1. Field of the Invention
The present invention relates to a jitter-detecting circuit, a receiving circuit including the jitter-detecting circuit, and a communication system. In particular, it relates to a jitter-detecting circuit for optimization of receiving sensitivity, a receiving circuit including the jitter-detecting circuit, and a communication system.
2. Description of the Prior Art
In general, a receiving-sensitivity control parameter for deciding the receiving sensitivity of an optical receiving circuit has the optimum value depending on the optical reception level. Receiving-sensitivity control parameters include parameters for enhancing of receiving sensitivity of the receiving circuit such as an input-signal identification level (identification voltage), identification phase, multiplication factor of an avalanche photodiode (APD), and frequency characteristic of an amplifying circuit such as a limiter amplifier, and parameters of means for compensating the waveform deterioration of a signal passing through a transmission line (optimization of optical input waveform input to receiving circuit) such as parameters for a dispersion compensator and preemphasis circuit at a transmission end.
These receiving-sensitivity control parameters have been used so far by adjusting them so that they become optimum at a certain point for convenience sake. FIG. 13 is a block diagram showing a configuration of a conventional optical receiving circuit. In FIG. 13, the conventional optical receiving circuit is constituted by a light receiving element 101, preamplifier 102, limiter amplifier 103, D-FF (D flip-flop) 104, and clock-extracting circuit (PLL circuit) 105.
An input signal supplied from the light receiving element 101 is amplified by the preamplifier 102 and input to the limiter amplifier 103. Then, the level of the input signal is compared with a constant identification voltage Vth 106 by the limiter amplifier 103 and “0” or “1” is determined. Then, a clock is extracted from a binary-equalizing-data signal which is the determination result by the clock-extracting circuit 105. Then, the binary-equalizing-data signal and clock are input to the D-FF 104 and output data is obtained.
Thus, even if the identification voltage Vth 106 is constant, it is sufficient for practical use because an S/N (signal-to-noise ratio) deterioration factor substantially consists of only the loss of a transmission line.
However, in the case of recent high-speed long-distance transmission including an optical amplifier and WDM (wavelength division multiplexing transmission), the tolerance to a shift of a receiving-sensitivity control parameter from the optimum position is lowered because there are a more number of factors causing the S/N of an optical input signal to deteriorate compared with a conventional optical transmission system, such as ASE (amplified spontaneous emission) noises generated by an optical-fiber amplifier, waveform deterioration caused by dispersion or nonlinear effect of an optical fiber, and crosstalk from an adjacent channel in wavelength multiplex transmission.
In the case of the above high-speed long-distance transmission system, the above method of fixedly providing receiving-sensitivity control parameters cannot ensure a required receiving sensitivity, and therefore, it has a disadvantage such as limited transmission distance. Moreover, a bent (floor) of an error-rate characteristic occurs because of shift of receiving-sensitivity control parameters from the optimum positions. The floor may narrow the dynamic range, and in the worst case, provide no error-free range.
There is the jitter of a binary-equalizing-data signal obtained by converting an input signal into a binary notation as a factor relating to a receiving sensitivity. The correlation between bit error rate (BER) showing a receiving sensitivity and jitter is briefly described below by referring to FIG. 14. FIG. 14 is an illustration showing a correlation between input power, bit error rate, and jitter. In FIG. 14, the horizontal axis shows input power, upward vertical axis shows bit error rate, and downward vertical axis shows jitter value. As shown in FIG. 14, as the input power decreases, the bit error rate increases and the jitter value also increases. Therefore, when the bit error rate increases, the jitter value increases. However, as the input power increases, the bit error rate decreases and the jitter value also decreases. Therefore, when the bit error rate decreases, the jitter value also decreases. Thus, because a bit error rate uniquely corresponds to a jitter value, it is possible to measure a receiving sensitivity by measuring a jitter value.